FIG. 1 illustrates a semiconductor device 110 containing a planar capacitor structure 114 formed over a substrate 112. The structure of FIG. 1 is not intended to represent a particular capacitor as constructed in a semiconductor device, but is merely used as an example to illustrate the main components of such a capacitor. Substrate 112 may be formed, for example, of silicon or silicon-on-insulator (SOI) material or other well known substrate material. A first conductive layer or bottom electrode 116 is formed over the substrate using materials and methods known in the art. For example, the first conductive layer may be formed of two layers: a polysilicon bottom layer with a hemispherical silicon grain, or HSG, layer atop the polysilicon.
The capacitor structure 114 may be coupled to an active region 113 in the substrate, for example a source or drain region of a MOS transistor. Alternately, the capacitor structure 114 may be insulated from the substrate 112 through an insulating region. A capacitor dielectric layer 118 is formed over the conductive layer 116, and may be formed of a substantially nonconductive material such as, for example, silicon nitride (Si3N4), or other dielectric material known in the art. A thin protective layer 119 is then formed over the dielectric layer using gaseous oxygen and hydrogen. The protective layer may thus comprise silicon dioxide (SiO2) which forms as the oxygen reacts with the silicon from the silicon nitride in the dielectric. The protective layer serves to “heal” any defects in the dielectric layer 118 which might cause leakage problems across the resulting capacitor. A second conductive layer or top electrode 122 is formed over the protective layer and may be formed with polysilicon or other conductive material.
In order to effectively utilize the capacitor 114 in modern dynamic random access memories (DRAMs), however, it has been necessary to reduce its size and substantially minimize the thickness of the dielectric layer 118. In many embodiments, it is therefore especially desirable that the dielectric layer be less than about 60 Angstroms in thickness, and even more desirably, less than about 50 Angstroms thick. Unfortunately, leakage current between the first and second conductive layers 116, 122 tends to increase exponentially as the thickness of the dielectric layer 118 is reduced to below 50 Angstroms. While formation of the protective layer 119 has been instrumental in helping to reduce this leakage current, there is still considerable need for a further reduction to enhance overall capacitor performance, as capacitor sizes continue to shrink in memory devices.
What is therefore needed in the art is a new method of forming a capacitor structure which results in reduced leakage current, while overall capacitance is substantially unaffected. Also needed are new capacitors in which leakage current between conductive layers is minimized, while capacitance is substantially maintained.